Electronics Engineer and Hobbyist.
Studying for a PhD in Electronic Engineering, I enjoy finding innovative solutions to technological problems.
2016 - Present
June 2018 - Present
I joined the Devices Circuits and Systems group of Arm Research in 2018 to complete my PhD within industry as part of the EPSRC iCASE programme. Leading the ‘COILS’ project (based on my PhD research, listed above) within Arm research, the key experience I developed includes:
October 2017 - October 2018
Supervising undergraduate students as a lab demonstrator, my main duties included: assessing practical lab work such as embedded systems design (PCB design, layout and assembly), embedded programming (AVR MCU - C/C++/Arm Assembly), and IC design (using Tanner Tools EDA suite).
October 2016 - June 2018
At the University of Southampton, I was the lead lecturer for several coursework modules including:
June 2015 - August 2015
Working as a placement student within the CPU design group, my role focussed on implementing commercial VIP in UVM-based System Verilog test-benches for validating AMBA bus functionality of a new L3 cache design. I also participated in Arm’s “Global Intern Innovation Challenge” and finished first place.
This paper presents a low-energy die-to-die inductive transceiver for use within a stacked 3D-IC. The design is implemented in a 2-tier 0.35µm CMOS test chip and demonstrates vertical communication at a rate of 133Mbps/channel, across a distance of 110µm, whilst consuming only 10.8pJ per transmitted bit. This represents a 5.3x improvement when compared to state-of-the-art inductive transceivers by combining: (1) 3-ary pulse-position modulation, to encode data in terms of the latency between sequential pulses (rather than using one-to-one pulsecode mappings), and (2) A tunable current driver circuit to adjust the transmit current dynamically based on the quality of the stacked die assembly.Download PDF
Recently, the use of wireless (or contactless) 3D integration has been proposed as a low-cost method of stacking disparate processing and sensor dies into singular, small formfactor ICs. Whilst such devices would be ideally suited for the Internet of Things (IoT), in the IoT, maintaining low-power consumption is of paramount importance. Contactless intertier links use signiﬁcant energy when forming a magnetic ﬁeld which can penetrate multiple silicon dies, and hence are often criticised for their poor power efﬁciency when compared to wired alternatives such as through silicon vias (TSVs). To address this, in this paper we present a novel, neuro-inspired, inductive transceiver (for transmitting data between tiers of a 3D-IC) that maintains low power consumption by encoding frames of data in terms of the latency between pulses, thereby reducing the number of transmit pulses and energy required per bit. The proposed approach is validated using commercial electromagnetic and electrical circuit simulators in 65nm CMOS technology. Results demonstrate an energy consumption of 0.79pJ/bit, representing a reduction of 31% when compared to existing state-of-the-art transceivers, or an increased communication distance of up to 1.8x for the same power budget.
Three dimensional system integration is a promising enabling technology for realising heterogeneous ICs, facilitating stacking of disparate elements such as MEMS, sensors, analogue components, memories and digital processing. Recently, research has looked to contactless 3D integration using inductive coupling links (ICLs) to provide a low-cost alternative to conventional contact-based approaches (e.g. through silicon vias) for 3D integration. In this paper, we present a novel, fully wireless, ICL architecture for Concurrent Data and Power Transfer (CoDAPT) between tiers of a 3D-IC. The proposed CoDAPT architecture uses only a single inductor for simultaneous power transmission and data communication, resulting in high area efficiency, whilst facilitating low-cost, straightforward die stacking. The proposed design is experimentally validated through full wave EM and SPICE simulation and demonstrates capability to communicate data vertically at a rate of 1.3Gbps/channel (utilising an area of only 0.052mm2) whilst simultaneously achieving power delivery of 0.83mW, under standard operating conditions. A case study is also presented, demonstrating that CoDAPT achieves an area reduction greater than 1.7x when compared with existing works, representing an important progression towards ultra low-cost 3D-ICs through fully wireless stacking.Download PDF
Recent research in the field of 3-D system integration has looked to the use of inductive-coupling links (ICLs) to provide vertical connectivity without incurring the inflated fabrication and testing costs associated with through-silicon vias. For power-efficient ICL design, optimization of the utilized physical inductor geometries is essential, but currently must be performed manually in a process that can take several hours. As a result, the generation of optimized inductor designs poses a significant challenge. In this paper, we address this challenge in three main contributions: 1) a novel, nonuniform planar inductor layout that exhibits enhanced performance when compared with conventional uniform inductors; 2) a rapid solver for evaluating inductor layouts; and 3) a high-speed optimization algorithm for determining best performing coil pairs. These three contributions are combined as a CAD tool for optimization of ICLs for 3-D-ICs (COIL-3-D). Results demonstrate that COIL-3-D achieves an average accuracy within 7.8% of finite-element tools consuming a small fraction of the time (1.5x 10E-3 %), significantly ameliorating the design of ICL-based 3-D-ICs. We also demonstrate that using COIL-3-D to optimize ICL inductor layouts can yield significant performance (up to 41.5% bandwidth improvement) and power (up to 8.1% power improvement) benefits, when compared with layouts used in prior ICL implementations. For these reasons, this paper unlocks new potential for low-cost, power-efficient 3-D integration using ICLs.Download PDF